Da ta S he et , D S 1 , F eb . 2 00 3
SBCX-X
S/T Bus Interface Circuit Extended
PEB 3081, Version 1.4
Wired
Communications
N e v e r
s t o p
t h i n k i n g .
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®,
FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®,
MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®, QUAT®, QuadFALC®,
SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG.
10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG.
Microsoft® is a registered trademark of Microsoft Corporation. Linux® is a registered
trademark of Linus Torvalds.
The information in this document is subject to change without notice.
Edition 2003-02-04
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide
(www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet
Revision History:
2003-02-04
Previous Version:
Data Sheet, DS1, V1.3, 2000-07-21
Page
Subjects (major changes since last revision)
Chapter 1 Comparison SBCX/SBCX-X
Chapter
3.3.6.2
S- Transceiver Synchronization New
Chapter
3.3.10
Test Functions extended
Chapter
3.7.1.1
CDA Handler Description extended
Chapter
3.7.5.1
TIC Bus Access Control: Note added
Chapter
5.6
IOM-2 Interface Timing: Explanation added
Chapter
5.9
S-Transceiver
Chapter
5.10
Recommended Transformer Specification: Changed
Chapter
5.11
Line Overload Protection added
Chapter
5.12
EMC/ESD added
DS 1
SBCX-X
PEB 3081
Table of Contents
Page
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.6.1
3.3.6.2
3.3.7
3.3.8
3.3.9
3.3.10
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.1.1
3.5.1.2
3.5.1.3
3.5.1.4
3.5.2
3.5.2.1
3.5.2.2
3.5.2.3
Description of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activation Indication via Pin ACL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T-Interface Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T-Interface Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer and Delay between IOM-2 and S/T . . . . . . . . . . . . . . . .
Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S-Transceiver Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T Interface Delay Compensation (TE/LT-T Mode) . . . . . . . . . . . . . . .
Level Detection Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transceiver Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of the Receive PLL (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Clock Output C768 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control of Layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Machine TE and LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Transition Diagram (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . .
States (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C/I Codes (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Infos on S/T (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Transition Diagram (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
States (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C/I Codes (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
4
11
14
15
16
23
23
25
26
27
29
31
33
35
36
38
40
42
45
46
47
47
49
50
50
50
51
53
56
56
57
58
60
60
62
64
66
67
67
68
69
2003-02-04
SBCX-X
PEB 3081
Table of Contents
Page
3.5.2.4
3.5.3
3.5.3.1
3.5.3.2
3.5.3.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
3.7
3.7.1
3.7.1.1
3.7.2
3.7.2.1
3.7.2.2
3.7.3
3.7.3.1
3.7.3.2
3.7.3.3
3.7.3.4
3.7.3.5
3.7.3.6
3.7.4
3.7.5
3.7.5.1
3.7.5.2
3.7.5.3
3.7.5.4
3.7.6
3.8
Infos on S/T (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
State Transition Diagram (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
States (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
C/I Codes (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Command / Indicate Channel Codes (C/I0) - Overview . . . . . . . . . . . . . 75
Control Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Example of Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Activation initiated by the Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Activation initiated by the Network Termination NT . . . . . . . . . . . . . . . . 78
IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Serial Data Strobe Signal and Strobed Data Clock . . . . . . . . . . . . . . . 94
Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Strobed IOM-2 Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
IOM-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
MONITOR Channel Programming as a Master Device . . . . . . . . . . 103
MONITOR Channel Programming as a Slave Device . . . . . . . . . . . 103
MONITOR Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
TIC Bus D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . 108
S-Bus Priority Mechanism for D-Channel . . . . . . . . . . . . . . . . . . . . 110
S-Bus D-Channel Control in LT-T . . . . . . . . . . . . . . . . . . . . . . . . . . 112
D-Channel Control in the Intelligent NT (TIC- and S-Bus) . . . . . . . . 112
Activation/Deactivation of IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . 116
Auxiliary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transceiver and C/I Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TR_MODE2 - Transceiver Mode Register 2 . . . . . . . . . . . . . . . . . . . .
CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . .
CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . .
CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . .
CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . .
TR_CONF0 - Transceiver Configuration Register 0 . . . . . . . . . . . . . .
TR_CONF1 - Transceiver Configuration Register 1 . . . . . . . . . . . . . .
TR_CONF2 - Transmitter Configuration Register 2 . . . . . . . . . . . . . .
TR_STA - Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
5
120
126
126
127
128
128
129
129
131
131
133
2003-02-04
SBCX-X
PEB 3081
Table of Contents
4.1.10
4.1.11
4.1.12
4.1.13
4.1.14
4.1.15
4.1.16
4.1.17
4.1.18
4.1.19
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
4.3.14
4.3.15
4.3.16
4.3.17
4.3.18
4.3.19
4.3.20
4.3.21
4.4
4.4.1
4.4.2
4.4.3
Page
TR_CMD - Transceiver Command Register . . . . . . . . . . . . . . . . . . . .
SQRR1 - S/Q-Channel Receive Register 1 . . . . . . . . . . . . . . . . . . . .
SQXR1- S/Q-Channel TX Register 1 . . . . . . . . . . . . . . . . . . . . . . . . .
SQRR2 - S/Q-Channel Receive Register 2 . . . . . . . . . . . . . . . . . . . . .
SQXR2 - S/Q-Channel TX Register 2 . . . . . . . . . . . . . . . . . . . . . . . . .
SQRR3 - S/Q-Channel Receive Register 3 . . . . . . . . . . . . . . . . . . . .
SQXR3 - S/Q-Channel TX Register 3 . . . . . . . . . . . . . . . . . . . . . . . . .
ISTATR - Interrupt Status Register Transceiver . . . . . . . . . . . . . . . . .
MASKTR - Mask Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . .
TR_MODE - Transceiver Mode Register 1 . . . . . . . . . . . . . . . . . . . . .
Auxiliary Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACFG1 - Auxiliary Configuration Register 1 . . . . . . . . . . . . . . . . . . . .
ACFG2 - Auxiliary Configuration Register 2 . . . . . . . . . . . . . . . . . . . .
AOE - Auxiliary Output Enable Register . . . . . . . . . . . . . . . . . . . . . . .
ARX - Auxiliary Interface Receive Register . . . . . . . . . . . . . . . . . . . .
ATX - Auxiliary Interface Transmit Register . . . . . . . . . . . . . . . . . . . .
IOM-2 and MONITOR Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . .
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . .
CDAx_CR - Control Register Controller Data Access CH1x . . . . . . .
TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0) . . .
TRC_CR - Control Register Transceiver C/I0 (IOM_CR.CI_CS=1) . . .
DCI_CR - Control Register for CI1 Handler (IOM_CR.CI_CS=0) . . . .
DCIC_CR - Control Register for CI0 Handler (IOM_CR.CI_CS=1) . . .
MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . .
SDSx_CR - Control Register Serial Data Strobe x . . . . . . . . . . . . . . .
IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . .
STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .
ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . .
MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . .
SDS_CONF - Configuration Register for Serial Data Strobes . . . . . .
MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . .
MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . .
MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . .
MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . .
MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . .
MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . .
Interrupt and General Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUXI - Auxiliary Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
6
134
135
136
136
137
137
137
137
138
139
140
140
140
141
141
142
142
142
143
144
145
146
146
147
148
149
150
152
153
153
154
155
155
155
156
156
157
157
158
158
159
159
2003-02-04
SBCX-X
PEB 3081
Table of Contents
Page
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
AUXM - Auxiliary Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMR - Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
160
162
163
163
164
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Transformer Specification . . . . . . . . . . . . . . . . . . . . . . .
Line Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMC / ESD Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
165
165
166
166
168
169
169
172
173
174
175
176
177
6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Data Sheet
7
2003-02-04
SBCX-X
PEB 3081
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Data Sheet
Page
Logic Symbol of the SBCX-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Applications of the SBCX-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Configuration of the SBCX-X (P-MQFP-44) . . . . . . . . . . . . . . . . . 17
Pin Configuration of the SBCX-X (P-TQFP-48) . . . . . . . . . . . . . . . . . . 18
Functional Block Diagram of the SBCX-X . . . . . . . . . . . . . . . . . . . . . . 24
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Timer Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ACL Indication of Activated Layer 1 on TE Side . . . . . . . . . . . . . . . . . 35
ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Wiring Configurations in User Premises . . . . . . . . . . . . . . . . . . . . . . . 37
S/T-Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 39
Data Delay between IOM-2 and S/T Interface (TE mode only) . . . . . . 42
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
(TE mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Delay between IOM-2 and S/T Interface with 8 IOM Channels
(LT-S/NT mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Delay between IOM-2 and S/T Interface with 3 IOM Channels and
Maximum Receive Delay (LT-S/NT mode only). . . . . . . . . . . . . . . . . . 44
Equivalent Internal Circuit of the Transmitter Stage . . . . . . . . . . . . . . 45
Equivalent Internal Circuit of the Receiver Stage . . . . . . . . . . . . . . . . 46
Connection of Line Transformers and Power Supply to the SBCX-X . 47
External Circuitry for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 48
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 49
Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clock System of the SBCX-X. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Phase Relationships of SBCX-X Clock Signals . . . . . . . . . . . . . . . . . . 56
Buffered Oscillator Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Layer-1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
State Transition Diagram (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . 61
State Transition Diagram of Unconditional Transitions (TE, LT-T) . . . 62
State Transition Diagram (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
State Transition Diagram (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Example of Activation/Deactivation Initiated by the Terminal . . . . . . . 76
8
2003-02-04
SBCX-X
PEB 3081
List of Figures
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Data Sheet
Page
Example of Activation/Deactivation initiated by the Terminal (TE).
Activation/Deactivation completely under Software Control . . . . . . . . 77
Example of Activation/Deactivation initiated by the Network Termination
(NT). Activation/Deactivation completely under Software Control . . . . 78
IOM“-2 Frame Structure in Terminal Mode. . . . . . . . . . . . . . . . . . . . . . 80
Multiplexed Frame Structure of the IOM-2 Interface
in Non-TE Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Architecture of the IOM Handler (Example Configuration). . . . . . . . . . 83
Data Access via CDAx1 and CDAx2 Register Pairs . . . . . . . . . . . . . . 85
Examples for Data Access via CDAxy Registers . . . . . . . . . . . . . . . . . 86
Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . 87
Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 88
Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . . 91
Examples for the Synchronous Transfer Interrupt Control with one
Enabled STIxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Strobed IOM-2 Bit Clock. Register SDS_CONF Programmed to 01H . 96
Examples of MONITOR Channel Applications in IOM-2 TE Mode . . . 97
MONITOR Channel Protocol (IOM-2) . . . . . . . . . . . . . . . . . . . . . . . . . 99
Monitor Channel, Transmission Abort Requested by the Receiver . . 102
Monitor Channel, Transmission Abort Requested by the Transmitter 102
Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . 102
MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
CIC Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Applications of TIC Bus in IOM-2 Bus Configuration . . . . . . . . . . . . . 108
Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . 109
Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . 110
D-Channel Access Control on the S-Interface . . . . . . . . . . . . . . . . . . 111
Data Flow for Collision Resolution Procedure in Intelligent NT . . . . . 115
Deactivation of the IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Activation of the IOM-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Register Mapping of the SBCX-X . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 169
IOM-2 Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
IOM-2 Timing (LT-S, LT-T, NT mode) . . . . . . . . . . . . . . . . . . . . . . . . 170
Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . 171
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Reset Signal RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Maximum Line Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Transformer Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
9
2003-02-04
SBCX-X
PEB 3081
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Data Sheet
Page
Comparison of the SBCX-X with the Previous Version SBCX . . . . . . . 11
SBCX-X Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . 19
Host Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Header Byte Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SBCX-X Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
S/Q-Bit Position Identification and Multiframe Structure . . . . . . . . . . . 40
Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Examples for Synchronous Transfer Interrupts . . . . . . . . . . . . . . . . . . 91
CDA Register Combinations with Correct Read/Write Access . . . . . . 93
Transmit Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Receive Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SBCX-X Configuration Settings in Intelligent NT Applications . . . . . . 113
AUX Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
IOM-2 Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10
2003-02-04
SBCX-X
PEB 3081
Overview
1
Overview
The S/T Bus Interface Circuit Extended (SBCX-X) implements the four-wire S/T interface
used to link voice/data ISDN terminals, network terminators and PBX trunk lines to a
central office. It is based on the SBCX PEB 2081, and provides enhanced features and
functionality.
The SBCX-X provides the electrical and functional link between the analog S/T interface
(compliant to the ITU recommendation I.430) and the IOM-2 interface.
It provides an S/T interface operating in TE, LT-T, LT-S, NT and intelligent NT modes, a
serial control interface (SCI) for host programming, three general purpose I/O pins and
one LED output which is capable to indicate the activation status of the S-interface
automatically or can be programmed by the host.
The SBCX-X is produced in advanced CMOS technology.
Table 1
Comparison of the SBCX-X with the Previous Version SBCX
SBCX-X PEB 3081
SBCX PEB 2081
Operating modes
TE, LT-T, LT-S, NT, Int. NT TE, LT-T, LT-S, NT
Supply voltage
3.3 V ± 5%
5 V ± 5%
Technology
CMOS
CMOS
Package
P-MQFP-44 / P-TQFP-48
P-LCC-28 / P-DIP-28
Transceiver
Transformer ratio for the
transmitter
receiver
1:1
1:1
2:1
2:1
Test Functions
- Analog loop (LP_A - bit
EXLP - bit, ARL)
- Analog loop (ARL)
Microcontroller Interface
Serial interface (SCI)
Not provided
Host programming
SCI or MON channel
(MONITOR slave mode)
MON channel
(MONITOR slave mode)
Command structure of the
register access
Header/address/data
Address/data
Crystal
7.68 MHz
7.68 MHz
Buffered 7.68 MHz output
Provided
Not provided
Data Sheet
11
2003-02-04
SBCX-X
PEB 3081
Overview
Table 1
Comparison of the SBCX-X with the Previous Version SBCX (cont’d)
SBCX-X PEB 3081
SBCX PEB 2081
Controller data access to
IOM-2 timeslots
All timeslots;
Not provided
various possibilities of data
access
Data control and
manipulation
Various possibilities of data Shifting B-channel to
control and data
channel 0 and direction
manipulation
control
(enable/disable, shifting,
looping, switching)
Auxiliary Interface
AUX0-2
(general purpose I/Os)
MAI0-7
(general purpose I/Os and
several mode dependent
functions)
IOM channel select
(LT modes)
Channel select pins
multiplexed on AUX0-2
X0-2
LED pin
ACL (host controlled or
automatic indication of
layer 1 activated state)
Not provided
Output pin for D-channel
active indication
Provided
Not provided
Control input pin for
D-channel inhibit
Provided
Not provided
Stop/Go bit output pin
Provided
Provided
IOM-2
IOM-2 Interface
Double clock (DCL),
Double clock (DCL),
bit clock (BCL),
bit clock (BCL)
serial data strobe 1 (SDS1)
serial data strobe 2 (SDS2)
Monitor channel
programming
Provided
(MON0, 1, 2, ..., 7)
Provided
(MON0 or 1)
C/I channels
CI0 (4 bit),
CI1 (4/6 bit)
CI0 (4 bit),
CI1 (6 bit)
Data Sheet
12
2003-02-04
SBCX-X
PEB 3081
Overview
Table 1
Comparison of the SBCX-X with the Previous Version SBCX (cont’d)
SBCX-X PEB 3081
SBCX PEB 2081
Layer 1 state machine
With changes for
correspondence with the
actual ITU specification
Layer 1 state machine
in software
Possible
Not possible
Reset Signals
RES input signal
RSTO output signal
RST input signal
Reset Sources
RES Input
Watchdog
C/I Code Change
EAW Pin
Software Reset
RST Input
C/I Code Change
Interrupt Output Signals
INT
Not provided
low active (open drain) by
default, reprogrammable to
high active (push-pull)
Pin SCLK
1.536 MHz
Data Sheet
512 kHz
13
2003-02-04
S/T Bus Interface Circuit Extended
SBCX-X
PEB 3081
Version 1.4
1.1
Features
• Full duplex 2B + D S/T interface transceiver according
to ITU-T I.430
• Successor of SBCX PEB 2081 in 3.3 V technology
• Conversion of the frame structure between the
S/T-interface and IOM-2
P-MQFP-44-2
• IOM-2 interface supporting TE, LT-T, LT-S, NT and
intelligent NT modes
P-MQFP-44
• Single and double clocks on IOM-2
• Two serial data strobe signals
• Serial control interface (SCI)
• Microcontroller access to all IOM-2 timeslots
• Monitor channel handler (master/slave)
• IOM-2 MONITOR and C/I-channel protocol to control
peripheral devices
• Receive timing recovery
• D-channel access control
• Activation and deactivation procedures with automatic P-TQFP-48
activation from power down state
• Access to S and Q bits of S/T-interface
• Adaptively switched receive thresholds
• 3 general purpose I/O pins multiplexed with channel select pins
• Three pins for D-channel active indication, Stop/Go bit output and E-bit control on S
• One programmable timer
• Watchdog timer
• Software Reset
• One LED pin automatically indicating layer 1 activated state
• Test loops
• Sophisticated power management for restricted power mode
Type
Package
PEB 3081 H
P-MQFP-44
PEB 3081 F
P-TQFP-48
Data Sheet
14
2003-02-04
SBCX-X
PEB 3081
Overview
• Power supply 3.3 V
• 3.3 V output drivers, inputs are 5 V safe
• Advanced CMOS technology
1.2
Logic Symbol
The logic symbol gives an overview of the SBCX-X functions. It must be noted that not
all functions are available simultaneously, but depend on the selected mode.
Pins which are marked with a “ * “ are multiplexed and not available in all modes.
IOM-2 Interface
+3.3V 0V
0V
2
DU
DD
FSC
DCL
BCL/ SDS1/2 VDD VSS TP
VDDA VSSA
SCLK
SCL
C768
SDR
Host
Interface
(SCI)
SDX
XTAL2
CS
XTAL1
INT
7.68 MHz output
7.68 MHz ± 100ppm
SR1
RES
SR2
RSTO
S Interface
SX1
SX2
D-channel
Active Indication
DCA
D-channel Inhibit
DCI
S/G Bit Output
SGO
MODE0
Mode
Setting
MODE1 / EAW
AUX0...2 *
CH0...2 *
General
purpose I/O
IOM channel
select
ACL
LED Output
3081_17
Auxiliary Interface
Figure 1
Data Sheet
Logic Symbol of the SBCX-X
15
2003-02-04
SBCX-X
PEB 3081
Overview
1.3
Typical Applications
The SBCX-X is designed for the user area of the ISDN basic access. By programming
the corresponding operating mode it may be used at both ends of these interfaces.
Figure 2 illustrates the general application fields of the SBCX-X:
•
•
•
•
ISDN terminals (TE mode)
ISDN network termination (NT) for a link between the S/T interface and the U interface
ISDN subscriber line termination (LT-S)
ISDN trunk line termination (LT-T), i.e. PBX connection to central office
S
TE(1)
LT-S
TE(8)
Network Terminator (NT)
S
U
TE (1)
NT 1
NT
T
TE(8)
NT 2
LT-S
NT 1
LT-T
NT
ITS04492
= SBCX-X
Figure 2
Data Sheet
Applications of the SBCX-X
16
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
2
Pin Configuration
VDD
VSS
XTAL1
VSS
XTAL2
SX2
SX1
VDDA
VSSA
SR2
SR1
P-MQFP-44
33 32 31 30 29 28 27 26 25 24 23
BCL / SCLK
DU
34
35
22
21
DD
FSC
36
20
37
38
19
18
SDS1
17
C768
SGO
13
44
12
VSS
Data Sheet
SDX
9 10 11
SCL
SDR
2 3 4 5 6 7 8
INT
n.c.
1
Figure 3
SDS2
43
VDD
MODE1 / EAW
ACL
16
15
14
AUX1
AUX0
DCI
DCA
VDD
VSS
MODE0
40
41
42
RES
RSTO
VSS
VDD
SBCX-X
PEB 3081
39
CS
TP
DCL
VSS
AUX2
3081_02.vsd
Pin Configuration of the SBCX-X (P-MQFP-44)
17
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
VSS
VDD
XTAL2
XTAL1
n.c.
VSS
SX2
SX1
VDDA
VSSA
SR2
SR1
P-TQFP-48
36 35 34 33 32 31 30 29 28 27 26 25
AUX1
AUX0
40
21
SDS1
20
19
18
SDS2
17
16
DCI
DCA
46
15
47
48
14
13
n.c.
VDD
41
42
43
SBCX-X
PEB 3081
2 3 4 5 6 7 8
INT
n.c.
1
Figure 4
Data Sheet
C768
SGO
VSS
9 10 11 12
SDX
44
45
SCL
SDR
MODE1 / EAW
ACL
n.c.
23
22
n.c.
MODE0
38
39
VDD
VSS
VDD
AUX2
VSS
DCL
VSS
24
RES
RSTO
DD
FSC
37
CS
TP
BCL / SCLK
DU
3081_01.vsd
Pin Configuration of the SBCX-X (P-TQFP-48)
18
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
Table 2
SBCX-X Pin Definitions and Functions
Pin No.
MQFP44
Symbol
Input (I)
Function
Output (O)
Open
Drain (OD)
TQFP48
Host Interface
9
10
SCL
I
SCL - Serial Clock
Clock signal of the SCI interface if a
serial interface is selected.
10
11
SDR
I
SDR - Serial Data Receive
Receive data line of the SCI interface if a
serial interface is selected.
11
12
SDX
OD
SDX - Serial Data Transmit
Transmit data line of the SCI interface if
a serial interface is selected.
3
3
CS
I
Chip Select
A low level indicates a microcontroller
access to the SBCX-X.
1
1
INT
O (OD)
Interrupt Request
INT becomes active (low) if the SBCX-X
requests an interrupt (open drain
characteristic).
The polarity can be reprogrammed to
high active with push-pull characteristic.
5
5
RES
I
Reset
A LOW on this input forces the SBCX-X
into a reset state.
IOM-2 Interface
37
40
FSC
I/O
Frame Sync
8-kHz frame synchronization signal.
38
41
DCL
I/O
Data Clock
IOM-2 interface clock signal (double
clock, e.g. 1.536 MHz in TE mode).
Data Sheet
19
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
Table 2
SBCX-X Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
Open
Drain (OD)
MQFP44
TQFP48
34
37
BCL/
SCLK
O
Bit Clock/S-Clock
TE-Mode:
Bit clock output, identical to IOM-2 data
rate (DCL/2).
LT-T Mode:
1.536 MHz output synchronous to
S-interface.
NT / LT-S Mode:
Bit clock output derived from the DCL
input clock divided by 2.
36
39
DD
I/O (OD)
Data Downstream
IOM-2 data signal in downstream
direction.
35
38
DU
I/O (OD)
Data Upstream
IOM-2 data signal in upstream direction.
19
21
SDS1
O
Serial Data Strobe 1
Programmable strobe signal for time slot
and/or D-channel indication on IOM-2.
18
20
SDS2
O
Serial Data Strobe 2
Programmable strobe signal for time slot
and/or D-channel indication on IOM-2.
Miscellaneous
28
29
31
32
SX1
SX2
O
O
S-Bus Transmitter Output (positive)
S-Bus Transmitter Output (negative)
32
33
35
36
SR1
SR2
I
I
S-Bus Receiver Input
S-Bus Receiver Input
25
27
XTAL1
I
26
28
XTAL2
O
Crystal 1
Connection for a crystal or used as
external clock input. 7.68 MHz clock or
crystal required.
Crystal 2
Connection for a crystal. Not connected if
an external clock is supplied to XTAL1
Data Sheet
20
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
Table 2
SBCX-X Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
Open
Drain (OD)
MQFP44
TQFP48
20
21
22
22
23
24
AUX0
AUX1
AUX2
I/O (OD)
I/O (OD)
I/O (OD)
TE-Mode:
Auxiliary Port 0 - 2 (input/output)
These pins are individually
programmable as general input/output.
The state of the pin can be read from
(input) / written to (output) a register.
LT-T/LT-S/NT Mode:
CH0-2 - IOM-2 Channel Select (input)
These pins select one of eight channels
on the IOM-2 interface.
42
45
MODE0
I
Mode 0 Select
A LOW selects TE-mode and a HIGH
selects LT-T / LT-S mode (see MODE1/
EAW).
43
46
MODE1
I
EAW
I
The pin function depends on the setting
of MODE0.
If MODE0=1: Mode 1 Select
A LOW selects LT-T mode and a HIGH
selects LT-S mode.
If MODE0=0: External Awake
If a falling edge on this input is detected,
the SBCX-X generates an interrupt and,
if enabled, a reset pulse.
6
6
RSTO
OD
Reset Output
Low active reset output, either from a
watchdog timeout or programmed by the
host.
17
19
C768
O
Clock Output
A 7.68 MHz clock is output to support
other devices. This clock is not
synchronous to the S interface.
14
16
DCA
O
DCA - D-Channel Active Indication
This pin provides an output of the
D-channel bits on the S-bus receive line.
Data Sheet
21
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
Table 2
SBCX-X Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Function
Input (I)
Output (O)
Open
Drain (OD)
MQFP44
TQFP48
15
17
DCI
I
DCI - D-Channel Inhibit
If this bit is set to ’1’ the E-bits are
inverted, i.e. the D-channel is blocked
(only in NT/LT-S mode). This pin has the
same function as the D-channel inhibit bit
(see TR_MODE.DCH_INH).
16
18
SGO
O
SGO - Stop/Go Bit Output
A S/G bit output with programmable
polarity and length (TR_CONF2 register)
is provided.
44
47
ACL
O
Activation LED
This pin can either function as a
programmable output or it can
automatically indicate the activated state
of the S interface by a logic ’0’.
An LED with pre-resistance may directly
be connected to ACL.
4
4
TP
I
Test Pin
Must be connected to VSS.
2
2, 9, 15, n.c.
30, 48
Not Connected
Power Supply
8, 13, 23, 8, 14,
41
25, 44
VDD
–
Digital Power Supply Voltage
(3.3 V ± 5 %)
31
VDDA
–
Analog Power Supply Voltage
(3.3 V ± 5 %)
7, 12, 24, 7, 13,
27, 39,
26, 29,
40
42, 43
VSS
–
Digital Ground
(0 V)
30
VSSA
–
Analog Ground
(0 V)
Data Sheet
34
33
22
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3
Description of Functional Blocks
3.1
General Functions and Device Architecture
Figure 5 shows the architecture of the SBCX-X containing the following functions:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
S/T-interface transceiver supporting TE, LT-T, LT-S, NT and intelligent NT modes
Serial Control Interface (SCI)
IOM-2 interface for terminal, linecard and NT applications, with single/double clock
Two serial data strobe signals
IOM handler with controller data access registers (CDA) allows flexible access to IOM
timeslots for reading/writing, looping and shifting data
Synchronous transfer interrupts (STI) allow controlled access to IOM timeslots
MONITOR channel handler on IOM-2 for master mode, slave mode or data exchange
C/I-Channel handler
D-channel access mechanism
3-pin auxiliary port for general purpose I/O pins or channel select pins
LED connected to pin ACL indicates S-interface activation status automatically or can
be controlled by the host
Output for D-channel active indication (output of received D-bits on S)
Stop/Go bit output with programmable polarity and length
D-channel inhibit input pin to control inversion of E-bits on S to block other terminals
Level detect circuit on the S interface reduces power consumption in power down
mode
Timer for periodic or single interrupts
Clock and timing generation
Digital PLL to synchronize the transceiver to the S/T interface
Buffered 7.68 MHz oscillator clock output allows connection of further devices and
saves another crystal on the system board
Reset generation (watchdog timer)
Data Sheet
23
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Peripheral Devices
IOM-2 Interface
IOM-2 Handler
S Transceiver
General
Purpose
I/Os
Auxiliary
Interface
MONITOR
Handler
TIC
C/I
DPLL
Serial Host Interface
(SCI)
Reset
Interrupt
generation
OSC
3081_18
Host
Figure 5
Data Sheet
Functional Block Diagram of the SBCX-X
24
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.2
Microcontroller Interface
The SBCX-X supports a serial micrcontroller interface. For applications where no
controller is connected to the SBCX-X programming is done via the IOM-2 MONITOR
channel from a master device. In such applications the SBCX-X operates in the IOM-2
slave mode (refer to the corresponding chapter of the IOM-2 MONITOR handler). This
mode is suitable for control functions (e.g. programming registers of the S/T transceiver),
but the bandwidth is not sufficient to transfer B- and D-channel data.
The interface selection is done by pinstrapping of the chip select signal CS (see
Table 3). The selection pins are evaluated when the reset input RES is active. For the
pin levels stated in the table the following is defined:
’High’: dynamic pin; value must be ’High’ only during reset
VSS: static pin; pin must statically be strapped to ’Low’ level
Table 3
Host Interface Selection
CS
Interface Mode
’High’
Serial Control Interface (SCI)
VSS
IOM-2 MONITOR Channel (Slave Mode)
The interfaces contain all circuitry necessary for the access to programmable registers.
The mapping of all these registers can be found in Chapter 4.
The microcontroller interface also provides an interrupt request at pin INT which is low
active by default but can be reprogrammed to high active, a reset input pin RES and a
reset output pin RSTO.
The interrupt request pin INT becomes active if the SBCX-X requests an interrupt and
this can occur at any time.
Data Sheet
25
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.2.1
Serial Control Interface (SCI)
The serial control interface (SCI) is compatible to the SPI interface of Motorola or
Siemens C510 family of microcontrollers.
The SCI consists of 4 lines: SCL, SDX, SDR and CS. Data is transferred via the lines
SDR and SDX at the rate given by SCL. The falling edge of CS indicates the beginning
of a serial access to the registers. The SBCX-X latches incoming data at the rising edge
of SCL and shifts out at the falling edge of SCL. Each access must be terminated by a
rising edge of CS. Data is transferred in groups of 8 bits with the MSB first.
Figure 6 shows the timing of a one byte read/write access via the serial control interface.
Write Access
CS
SCL
Header
SDR
Address
Data
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
'0'
write
SDX
Read Access
CS
SCL
Header
SDR
Address
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
'1'
read
Data
7 6 5 4 3 2 1 0
SDX
21150_19
Figure 6
Data Sheet
Serial Control Interface Timing
26
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.2.2
Programming Sequences
The basic structure of a read/write access to the SBCX-X registers via the serial control
interface is shown in Figure 7.
write sequence:
write
byte 2
0
header
SDR
7
address
0 7 6
read sequence:
byte 3
write data
0 7
0
read
byte 2
header
SDR
7
1
address
0 7 6
0 7
SDX
Figure 7
byte 3
0
read data
Serial Control Interface Timing
A new programming sequence starts with the transfer of a header byte. The header byte
specifies different programming sequences allowing a flexible and optimized access to
the individual functional blocks of the SBCX-X.
The possible sequences for access to the complete address range 00H-7FH are listed in
Table 4 and described after that.
Table 4
Header
Byte
Header Byte Code
Sequence
40H/44H
48H/4CH
Alternating Read/Write (non-interleaved)
Adr-Data-Adr-Data
43H/47H
41H/45H
49H/4DH
Sequence Type
Alternating Read/Write (interleaved)
Read-only/Write-only (constant address)
Adr-Data-Data-Data
Read and following Write-only (non-interleaved)
Read and following Write-only (interleaved)
Note: In order to access the address range 00H-7FH bit 2 of the header byte must be set
to ’0’ (header bytes 40H, 48H, 43H, 41H, 49H), and for the addresses 80H-FFH bit 2
must be set to ’1’ (header bytes 44H, 4CH, 47H, 45H, 4DH).
Data Sheet
27
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Header 40H: Non-interleaved A-D-A-D Sequences
The non-interleaved A-D-A-D sequence gives direct read/write access to the complete
address range and can have any length. In this mode SDX and SDR can be connected
together allowing data transmission on one line.
Example for a read/write access with header 40H:
SDR header wradr wrdata
rdadr
SDX
rdadr
rddata
wradr wrdata
rdata
Header 48H: Interleaved A-D-A-D Sequences
The interleaved A-D-A-D sequence gives direct read/write access to the complete
address range and can have any length. This mode allows a time optimized access to
the registers by interleaving the data on SDX and SDR (SDR and SDX must not be
connected together).
Example for a read/write access with header 48H:
SDR header wradr wrdata
rdadr
SDX
rdadr
wradr wrdata
rddata rddata
Header 43H: Read-/Write- only A-D-D-D Sequence (Constant Address)
This mode can be used for a fast access to the HDLC FIFO data. Any address (rdadr,
wradr) in the range 00H-1FH and 6AH/7AH gives access to the current FIFO location
selected by an internal pointer which is automatically incremented with every data byte
following the first address byte. The sequence can have any length and is terminated by
the rising edge of CS.
Example for a write access with header 43H:
SDR header wradr wrdata wrdata wrdata wrdata wrdata wrdata wrdata
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
SDX
Example for a read access with header 43H:
SDR header rdadr
SDX
rddata rddata rddata rddata rddata rddata rddata
(rdadr)
Data Sheet
(rdadr)
(rdadr)
28
(rdadr)
(rdadr)
(rdadr)
(rdadr)
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Header 41H: Non-interleaved A-D-D-D Sequence
This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D
read access. This mode is useful for reading status information before writing to the
HDLC XFIFO. The termination condition of the read access is the reception of the wradr.
The sequence can have any length and is terminated by the rising edge of CS.
Example for a read/write access with header 41H:
SDR header rdadr
wradr wrdata wrdata wrdata
rdadr
(wradr)
SDX
rddata
(wradr)
(wradr)
rddata
Header 49H: Interleaved A-D-D-D Sequence
This sequence allows in front of the A-D-D-D write access an interleaved A-D-A-D read
access. This mode is useful for reading status information before writing to the HDLC
XFIFO. The termination condition of the read access is the reception of the wradr. The
sequence can have any length and is terminated by the rising edge of the CS line.
Example for a read/write access with header 49H:
SDR header rdadr
rdadr
wradr wrdata wrdata wrdata
(wradr)
SDX
3.2.3
(wradr)
(wradr)
rddata rddata
Interrupt Structure
Special events in the device are indicated by means of a single interrupt output, which
requests the host to read status information from the device or transfer data from/to the
device.
Since only one interrupt request pin (INT) is provided, the cause of an interrupt must be
determined by the host reading the interrupt status registers of the device.
The structure of the interrupt status registers is shown in Figure 8.
Data Sheet
29
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
MASK
ISTA
ST
ST
CIC
CIC
AUX
AUX
TRAN
TRAN
MOS
MOS
MSTI
STI
STOV21
STOV21
ASTI
STOV20
STOV20
STOV11
STOV11
STOV10
STOV10
STI21
STI21
ACK21
STI20
STI20
ACK20
STI11
STI11
ACK11
STI10
STI10
ACK10
CIR0
CIC0
CI1E
CIC1
EAW
EAW
LD
WOV
WOV
RIC
RIC
SQC
SQC
TIN
AUXM
TIN
AUXI
LD
SQW
MASKTR
Interrupt
CIX1
MRE
SQW
ISTATR
MDR
MER
Figure 8
MIE
MDA
MOCR
MAB
MOSR
3081_16.vsd
Interrupt Status and Mask Registers
All five interrupt bits in the ISTA register point at interrupt sources in the Monitor handler
(MOS), C/I handler (CIC), the transceiver (TRAN), the synchronous transfer (ST) and the
auxiliary interrupts (AUXI).
All these interrupt sources are described in the corresponding chapters. After the device
has requested an interrupt activating the interrupt pin (INT), the host must read first the
device interrupt status register (ISTA) in the associated interrupt service routine. The
interrupt pin of the device remains active until all interrupt sources are cleared by reading
the corresponding interrupt register. Therefore it is possible that the interrupt pin is still
active when the interrupt service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FFH into the MASK register)
and write back the old mask to the MASK register.
Data Sheet
30
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.2.4
Reset Generation
Figure 9 shows the organization of the reset generation of the device.
.
C/I Code Change
(Exchange Awake)
RSS1
125µs £ t £ 250µs
³1
EAW
(Subscriber Awake)
125µs £ t £ 250µs
'0'
'1x'
'1'
'01'
'00'
³1
Software Reset
Register (SRES)
' 01 '
RSS2,1
125µs £ t £ 250µs
Watchdog
(reserved)
RSS2,1
³1
Pin
RSTO
125µs £ t £ 250µs
Transceiver, C/I (22H-3FH)
Reset
IOM-2 (40H-5BH)
Functional
MON-channel (5CH-5FH)
Block
General Config (60H-6FH)
Reset MODE1 Register
Pin
RES
Internal Reset of all Registers
3081_21
Figure 9
Reset Generation
Reset Source Selection
The internal reset sources C/I code change, EAW and Watchdog can be output at the
low active reset pin RSTO. The selection of these reset sources can be done with the
RSS2,1 bits in the MODE1 register according Table 5.
The setting RSS2,1 = ’01’ is reserved for further use. In this case no reset except
software reset (SRES.RSTO) is output on RSTO. The internal reset sources set the
MODE1 register to its reset value.
Data Sheet
31
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Table 5
Reset Source Selection
RSS2
Bit 1
RSS1
Bit 0
C/I Code
Change
EAW
Watchdog
Timer
0
0
--
--
--
0
1
1
0
x
x
--
1
1
--
--
x
reserved
• C/I Code Change (Exchange Awake)
A change in the downstream C/I channel (C/I0) generates an external reset pulse of
125 µs £ t £ 250 µs.
• EAW (Subscriber Awake)
A low level on the EAW input starts the oscillator from the power down state and
generates a reset pulse of 125 µs £ t £ 250 µs.
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:
1.
2.
WTC1
WTC2
1
0
0
1
If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset pulse
of 125 µs is generated.
Deactivation of the watchdog timer is only possible with a hardware reset.
External Reset Input
At the RES input an external reset can be applied forcing the device in the reset state.
This external reset signal is additionally fed to the RSTO output. The length of the reset
signal is specified in Chapter 5.8.
After an external reset from the RES pin all registers of the device are set to its reset
values (see register description in Chapter 4).
Software Reset Register (SRES)
Every main functional block of the device can be reset separately by software setting the
corresponding bit in the SRES register. A reset to external devices can also be controlled
in this way. The reset state is activated by setting the corresponding bit to ’1’ and onchip
Data Sheet
32
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
logic resets this bit again automatically after 4 BCL clock cycles. The address range of
the registers which will be reset at each SRES bit is listed in Figure 9.
3.2.5
Timer Modes
The SBCX-X provides one timer which can be used for various purposes. It provides two
modes (Table 6), a count down timer interrupt, i.e. an interrupt is generated only once
after expiration of the selected period, and a periodic timer interrupt, which means an
interrupt is generated continuously after every expiration of that period.
Table 6
Address
65H
SBCX-X Timer
Register
TIMR
Modes
Period
Periodic
1 ... 63 ms
Count Down
1 ... 63 ms
When the programmed period has expired an interrupt is generated and indicated in the
auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from
AUXI.TIN and masked in AUXM.
MASK
ST
CIC
AUX
TRAN
MOS
ISTA
AUXM
EAW
WOV
TIN
ST
CIC
AUX
TRAN
MOS
AUXI
EAW
WOV
TIN
Interrupt
Figure 10
Data Sheet
Timer Interrupt Status Registers
33
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
The host starts and stops the timer in TIMR.CNT (Figure 11). If TIMR.TMD=0 the timer
is operating in count down mode, for TIMR.TMD=1 a periodic interrupt AUXI.TIN is
generated. The timer length (for count down timer) or the timer period (for periodic timer),
respectively, can be configured to a value between 1 - 63 ms (TIMR.CNT).
Timer Mode
0 : Count Down Timer
1 : Periodic Timer
Timer Count
0 : Timer off
1 ... 63 : 1 ... 63 ms
7
TIMR
Figure 11
Data Sheet
6
5
TMD 0
4
3
2
1
0
65H
CNT
3081_14
Timer Register
34
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.2.6
Activation Indication via Pin ACL
The activated state of the S-interface is directly indicated via pin ACL (Activation LED).
An LED with pre-resistance may directly be connected to this pin and a low level is driven
on ACL as soon as the layer 1 state machine reaches the activated state (see
Figure 12).
Figure 12
ACL Indication of Activated Layer 1 on TE Side
By default (ACFG2.ACL=0) the state of layer 1 is indicated at pin ACL. If the automatic
indication of the activated layer 1 is not required, the state on pin ACL can also be
controlled by the host (see Figure 13).
If ACFG2.ACL=1 the LED on pin ACL can be switched on (ACFG2.LED=1) and off
(ACFG2.LED=0) by the host.
+3.3V
'1'
ACL
ACFG2:LED
0 : off
1 : on
'0'
Layer 1
S Interface
ACFG2:ACL
3086_15
Figure 13
Data Sheet
ACL Configuration
35
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3
S/T-Interface
The layer-1 functions for the S/T interface of the SBCX-X are:
– line transceiver functions for the S/T interface according to the electrical specifications
of ITU-T I.430;
– conversion of the frame structure between IOM-2 and S/T interface;
– conversion from/to binary to/from pseudo-ternary code;
– level detection;
– receive timing recovery for point-to-point, passive bus and extended passive bus
configuration;
– S/T timing generation using IOM-2 timing synchronous to system, or vice versa;
– D-channel access control and priority handling;
– D-channel echo bit generation by handling of the global echo bit;
– activation/deactivation procedures, triggered by primitives received over the IOM-2
interface or by INFOs received from the line;
– execution of test loops.
The wiring configurations in user premises, in which the SBCX-X can be used, are
illustrated in Figure 14.
Data Sheet
36
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
£ 1000 m 1)
SBCX-X
TR
TR
TE
SBCX-X
LT-S
£ 1000 m 1)
SBCX-X
TR
TR
SBCX-X
LT-T
Point-to-Point
Configurations
NT
1) The maximum line attenuation tolerated by the SBCX-X is 7 dB at 96 kHz.
£ 100 m
TR
TR
£ 10 m
SBCX-X
....
TE1
SBCX-X
Short
Passive Bus
NT / LT-S
SBCX-X
TE8
£ 500 m
£ 25 m
TR
TR
£ 10 m
SBCX-X
TE1
Figure 14
Data Sheet
....
SBCX-X
Extended
Passive Bus
NT / LT-S
TR: Terminating Resistor
SBCX-X
TE8
3081_20
Wiring Configurations in User Premises
37
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.1
S/T-Interface Coding
Transmission over the S/T-interface is performed at a rate of 192 kbit/s. 144 kbit/s are
used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance
information.
Line Coding
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
For the required frame structure a code violation is indicated by two consecutive pulses
of the same polarity. These two pulses can be adjacent or separated by binary ONEs.
In bus configurations a binary ZERO always overwrites a binary ONE.
0 1 1
code violation
Figure 15
S/T-Interface Line Code
Frame Structure
Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data
(B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 16).
In the direction TE ® NT the frame is transmitted with a two bit offset. For details on the
framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the
standard frame structure for both directions (NT ® TE and TE ® NT) with all framing
and maintenance bits.
Data Sheet
38
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Figure 16
Frame Structure at Reference Points S and T (ITU I.430)
– F
Framing Bit
F = (0b) ® identifies new frame (always
positive pulse, always code violation)
– L.
D.C. Balancing Bit
L. = (0b) ® number of binary ZEROs sent
after the last L. bit was odd
– D
D-Channel Data Bit
Signaling data specified by user
– E
D-Channel Echo Bit
E = D ® received E-bit is equal to transmitted
D-bit
– FA
Auxiliary Framing Bit
See section 6.3 in ITU I.430
– N
N = FA
– B1
B1-Channel Data Bit
User data
– B2
B2-Channel Data Bit
User data
– A
Activation Bit
A = (0b) ® INFO 2 transmitted
A = (1b) ® INFO 4 transmitted
– S
S-Channel Data Bit
S1 channel data (see note below)
– M
Multiframing Bit
M = (1b) ® Start of new multiframe
Note: The ITU I.430 standard specifies S1 - S5 for optional use.
Data Sheet
39
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.2
S/T-Interface Multiframing
According to ITU recommendation I.430 a multiframe provides extra layer 1 capacity in
the TE-to-NT direction by using an extra channel between the TE and NT (Q-channel).
The Q bits are defined to be the bits in the FA bit position.
In the NT-to-TE direction the S-channel bits are used for information transmission. One
S channel (S1) out of five possible S-channels can be accessed by the SBCX-X.
In the NT-to-TE direction the S-channel bits are used for information transmission.
The S and Q channels are accessed via the µC interface or the IOM-2 MONITOR
channel, respectively, by reading/writing the SQR or SQX bits in the S/Q channel
registers (SQRRx, SQXRx).
Table 7 shows the S and Q bit positions within the multiframe.
Table 7
S/Q-Bit Position Identification and Multiframe Structure
Frame Number
NT-to-TE
NT-to-TE
FA Bit Position M Bit
NT-to-TE
S Bit
TE-to-NT
FA Bit Position
1
2
3
4
5
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
S11
S21
S31
S41
S51
Q1
ZERO
ZERO
ZERO
ZERO
6
7
8
9
10
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S12
S22
S32
S42
S52
Q2
ZERO
ZERO
ZERO
ZERO
11
12
13
14
15
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S13
S23
S33
S43
S53
Q3
ZERO
ZERO
ZERO
ZERO
16
17
18
19
20
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S14
S24
S34
S44
S54
Q4
ZERO
ZERO
ZERO
ZERO
1
2
ONE
ZERO
ONE
ZERO
S11
S21
Q1
ZERO
Data Sheet
40
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
TE Mode
After multiframe synchronization has been established, the Q data will be inserted at the
upstream (TE ® NT) FA bit position in each 5th S/T frame (see Table 7).
When synchronization is not achieved or lost, each received FA bit is mirrored to the next
transmitted FA bit.
Multiframe synchronization is achieved after two complete multiframes have been
detected with reference to FA/N bit and M bit positions. Multiframe synchronization is lost
if bit errors in FA/N bit or M bit positions have been detected in two consecutive
multiframes. The synchronization state is indicated by the MSYN bit in the S/Q-channel
receive register (SQRR1).
The multiframe synchronization can be enabled or disabled by programming the MFEN
bit in the S/Q-channel transmit register (SQXR1).
NT Mode
The transceiver in NT mode starts multiframing if SQXR1.MFEN is set.
After multiframe synchronization has been established in the TE, the Q data will be
inserted at the upstream (TE ® NT) FA bit position by the TE in each 5th S/T frame, the
S data will be inserted at the downstream (NT ® TE) S bit position in each S/T frame
(see Table 7).
Interrupt Handling for Multiframing
To trigger the microcontroller for a multiframe access an interrupt can be generated once
per multiframe (SQW) or if the received S-channels (TE) or Q-channel (NT) have
changed (SQC).
In both cases the microcontroller has access to the multiframe within the duration of one
multiframe (5 ms).
Data Sheet
41
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.3
Data Transfer and Delay between IOM-2 and S/T
TE mode
In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register TR_CMD is programmed to ’011’ the B1, B2, D and E bits are transferred
transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted
to the IOM-2 interface.
To transfer data transparently to the S/T interface any activation request C/I command
(AR8, AR10 or ARL) is additionally necessary or if the internal layer-1 statemachine is
disabled, bit TDDIS of register TR_CMD has additionally to be programmed to ’0’.
Figure 17 shows the data delay between the IOM-2 and the S/T interface and vice
versa.
For the D channel the delay from the IOM-2 to the S/T interface is only valid if S/G
evaluation is disabled (TR_MODE2.DIM0=0). If S/G evaluation is enabled
(TR_MODE2.DIM2-0=0x1) the delay depends on the selected priority and the relation
between the echo bits on S and the D channel bits on the IOM-2, e.g. for priority 8 the
timing relation between the 8th D-bit on S bus and the D-channel on IOM-2.
E
NT -> TE
F
D
E
B1
B2
D
TE -> NT
F
B1
B2
D
E
D
E
B1
B2
D
D
B1
D
E
F
E
B1
D
B2
D
F
B2
D
B1
B2
D
E
D
E
B1
B2
D
D
B1
D
D
B2
FSC
DU
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
DD
B1 B2 D
Figure 17
Data Sheet
E
B1 B2 D
E
B1 B2 D
E
B1 B2 D
E
line_iom_s.vsd
Data Delay between IOM-2 and S/T Interface (TE mode only)
42
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
E
NT -> TE
F
D
E
B1
B2
D
TE -> NT
F
B1
B2
D
E
D
E
B1
B2
D
D
B1
D
E
F
E
B1
D
B2
D
F
B2
D
B1
D
E
D
E
B1
B2
D
D
B2
B1
D
D
B2
FSC
DU
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
DD
B1 B2 D
E
B1 B2 D
E
B1 B2 D
E
B1 B2 D
Mapping of B-Channel Timeslots
Mapping of a 4-bit group of D-bits on S and IOM depends on prehistory (e.g. priority control):
1. Possibility
2. Possibility
Figure 18
E
line_iom_s_dch.vsd
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
(TE mode only)
LT-T mode
In this mode the frame relation between S/T interface and IOM-2 is flexible.
LT-S/NT mode
In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register TR_CMD is programmed to ’011’ the B1, B2 and D bits are transferred
transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted
to the IOM-2 interface.
Note: In intelligent NT the D-channel access can be blocked by the IOM-2 D-channel
handler.
Data Sheet
43
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
E
NT -> TE
F
D
E
B1
D
B2
D
F
TE -> NT
B1
E
D
E
B1
B2
D
D
B2
B1
D
E
F
D
B1
D
B2
D
B2
E
D
F
B1
E
D
E
B1
B2
D
D
B2
B1
D
D
B2
FSC
DD
B1 B2
D
B1 B2
D
B1 B2
D
B1 B2
D
B1 B2
D
B1 B2
D
B1 B2
D
B1 B2
D
DU
Figure 19
Data Delay between IOM-2 and S/T Interface with 8 IOM Channels
(LT-S/NT mode only)
E
NT -> TE
F
D
E
B1
D
B2
D
F
TE -> NT
line_iom_s4nt.vsd
B1
B2
E
F
B1
E
B1
B2
D
D
B1
D
TE -> NT (42µs)
D
E
F
D
B2
F
D
B2
D
B1
B2
D
D
D
B1
E
B1
D
D
B2
D
B2
F
B1
E
D
E
B1
B2
D
D
B1
D
B2
D
B2
D
D
B1
D
B2
FSC
DU
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
DD
B1 B2 D
Figure 20
Data Sheet
E
B1 B2 D
E
B1 B2 D
E
B1 B2 D
E
line_iom_s4nt_dly.vsd
Data Delay between IOM-2 and S/T Interface with 3 IOM Channels and
Maximum Receive Delay (LT-S/NT mode only)
44
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.4
Transmitter Characteristics
The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter
which is realized as a symmetrical current limited voltage source (VSX1/SX2 = +/-1.05 V;
Imax = 26 mA). The equivalent circuit of the transmitter is shown in Figure 21.
The nominal pulse amplitude on the S-interface of 750 mV (zero-peak) is adjusted with
external resistors (see Chapter 3.3.6.1).
VCM+0.525V
VCM
VCM-0.525V
'+0'
'1'
'-0'
+
SX1
V=1
-
Level
VCM-0.525V
VCM
VCM+0.525V
Figure 21
Data Sheet
'+0'
'1'
VCM
TR_CONF2.DIS_TX
'+0' '1' '-0'
-
SX2
V=1
+
'-0'
21150_28
Equivalent Internal Circuit of the Transmitter Stage
45
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.5
Receiver Characteristics
The receiver consists of a differential input stage, a peak detector and a set of
comparators. Additional noise immunity is achieved by digital oversampling after the
comparators. A simplified equivalent circuit of the receiver is shown in Figure 22.
100 kW
10 kW
SR1
40 kW
VrefLD
Level detected
Vrefmin
10 kW
SR2
40 kW
VCM
Vref+
Positive detected
Peak
Detector Vref-
Negative detected
reccirc
Figure 22
Equivalent Internal Circuit of the Receiver Stage
The input stage works together with external 10 kW resistors to match the input voltage
to the internal thresholds. The data detection threshold Vref is continuously adapted
between a maximal (Vrefmax) and a minimal (Vrefmin) reference level related to the line
level. The peak detector requires maximum 2 ms to reach the peak value while storing
the peak level for at least 250 ms (RC > 1 ms).
The additional level detector for power up/down control works with a fixed threshold
VrefLD. The level detector monitors the line input signals to detect whether an INFO is
present. When closing an analog loop it is therefore possible to indicate an incoming
signal during activated loop.
Data Sheet
46
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.6
S/T Interface Circuitry
For both, receive and transmit direction a 1:1 transformer is used to connect the SBCXX transceiver to the 4 wire S/T interface. Typical transformer characteristics can be found
in the chapter on electrical characteristics. The connections of the line transformers is
shown in Figure 23.
3.3 V
1:1
SX1
VDD
Protection
Circuit
Transmit
Pair
SX2
10 µF
1:1
SR1
Protection
Circuit
VSS
GND
Receive
Pair
SR2
21150_05
Figure 23
Connection of Line Transformers and Power Supply to the SBCX-X
For the transmit direction an external transformer is required to provide isolation and
pulse shape according to the ITU-T recommendations.
3.3.6.1
External Protection Circuitry
The ITU-T I.430 specification for both transmitter and receiver impedances in TEs results
in a conflict with respect to external S-protection circuitry requirements:
– To avoid destruction or malfunction of the S-device it is desirable to drain off even
small overvoltages reliably.
– To meet the 96 kHz impedance test specified for transmitters and receivers (for TEs
only, ITU-T I.430 sections 8.5.1.2a and 8.6.1.1) the protection circuit must be
dimensioned such that voltages below 1.2 V (ITU-T I.430 amplitude) x transformer
ratio are not affected.
This requirement results from the fact that this test is also to be performed with no supply
voltage being connected to the TE. Therefore the second reference point for
overvoltages VDD, is tied to GND. Then, if the amplitude of the 96 kHz test signal is
greater than the combined forward voltages of the diodes, a current exceeding the
specified one may pass the protection circuit.
The following recommendations aim at achieving the highest possible device protection
against overvoltages while still fulfilling the 96 kHz impedance tests.
Data Sheet
47
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Protection Circuit for Transmitter
SX1
1:1
R
S Bus
Vdd
SX2
R
3081_23
Figure 24
External Circuitry for Transmitter
Figure 24 illustrates the secondary protection circuit recommended for the transmitter.
The external resistors (R = 5 .... 10 W) are required in order to adjust the output voltage
to the pulse mask on the one hand and in order to meet the output impedance of
minimum 20 W (transmission of a binary zero according to ITU-T I.430) on the other
hand.
Two mutually reversed diode paths protect the device against positive or negative
overvoltages on both lines.
An ideal protection circuit should limit the voltage at the SX pins from – 0.4 V to VDD
+ 0.4 V. With the circuit in Figure 24 the pin voltage range is increased from – 1.4 V to
VDD + 0.7 V. The resulting forward voltage of 1.4 V will prevent the protection circuit from
becoming active if the 96 kHz test signal is applied while no supply voltage is present.
Protection Circuit for Receiver
Figure 25 illustrates the external circuitry used in combination with a symmetrical
receiver. Protection of symmetrical receivers is rather simple.
1:1
S Bus
Note: up to 10 pF capacitors are optional for noise reduction
Figure 25
Data Sheet
External Circuitry for Symmetrical Receivers
48
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Between each receive line and the transformer a 10 kW resistor is used. This value is
split into two resistors: one between transformer and protection diodes for current limiting
during the 96 kHz test, and the second one between input pin and protection diodes to
limit the maximum input current of the chip.
With symmetrical receivers no difficulties regarding LCL measurements are observed;
compensation networks thus are obsolete.
In order to comply to the physical requirements of ITU-T recommendation I.430 and
considering the national requirements concerning overvoltage protection and
electromagnetic compatibility (EMC), the SBCX-X may need additional circuitry.
3.3.6.2
S-Transceiver Synchronization
Synchronization problems can occur on a S-Bus that is not terminated properly.
Therefore, it is recommended to change the resistor values in the receive path. The sum
of both resistors is increased from 10 kW (1.8 + 8.2) to e.g. 34 kW (6.8 + 27) for either
receiver line. This change is possible but not necessary for a S-Bus that is terminated
properly.
R1
R2
SR2
GND
VDD
1:1
S Bus
SR1
R1
R2
21150_33
Note: Capacitors (up to 10 pF) are optional for noise reduction.
Figure 26
External Circuitry for Symmetrical Receivers
Note: Lower or higher values than 34 kW may be used as well, however for values above
34 kW the additional delay must be compensated by setting TR_CONF2.PDS=1
(compensates 260 ns) so the allowed input phase delay is not violated.
Data Sheet
49
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.7
S/T Interface Delay Compensation (TE/LT-T Mode)
The S/T transmitter is shifted by two S/T bits minus 7 oscillator periods (plus analog
delay plus delay of the external circuitry) with respect to the received frame. To
compensate additional delay introduced into the receive and transmit path by the
external circuit the delay of the transmit data can be reduced by another two oscillator
periods (2 x 130 ns). Therefore PDS of the TR_CONF2 register must be programmed to
’1’. This delay compensation might be necessary in order to comply with the "total phase
deviation input to output" requirement of ITU-T recommendation I.430 which specifies a
phase deviation in the range of – 7% to + 15% of a bit period.
3.3.8
Level Detection Power Down
If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas
if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks,
including the IOM-2 interface, are stopped (DD, DU are ’high’, DCL and BCL are ’low’).
An activation initiated from the exchange side will have the consequence that a clock
signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set
to ’1’ the microcontroller has to take care of an interrupt caused by the level detect circuit
(ISTATR.LD)
From the terminal side an activation must be started by setting and resetting the SPU-bit
in the IOM_CR register and writing TIM to the CIX0 register or by resetting
MODE1.CFS=0.
3.3.9
Transceiver Enable/Disable
The layer-1 part of the SBCX-X can be enabled/disabled by configuration (see
Figure 27) with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX .
By default all layer-1 functions with the exception of the transmitter buffer is enabled
(DIS_TR = ’0’, DIS_TX = ’1’). With several terminals connected to the S/T interface,
another terminal may keep the interface activated although the SBCX-X does not
establish a connection. The receiver will monitor for incoming calls in this configuration.
If the transceiver is disabled (DIS_TR = ’1’) all layer-1 functions are disabled including
the level detection circuit of the receiver. In this case the power consumption of the
Layer-1 is reduced to a minimum. The DCL and FSC pins become input.
Data Sheet
50
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
TR_CONF0.DIS_TR
TR_CONF2.DIS_TX
’1’
’0’
Figure 27
3.3.10
Disabling of S/T Transmitter
Test Functions
The SBCX-X provides test and diagnostic functions for the S/T interface:
Note: For more details please refer to the application note “Test Function of new STransceiver family”
– The internal local loop (internal Loop A) is activated by a C/I command ARL or by
setting the bit LP_A (Loop Analog) in the TR_CMD register if the layer-1 statemachine
is disabled.
The transmit data of the transmitter is looped back internally to the receiver. The data
of the IOM-2 input B- and D-channels are looped back to the output B- and Dchannels.
The S/T interface level detector is enabled, i.e. if a level is detected this will be
reported by the Resynchronization Indication (RSY) but the loop function is not
affected.
Depending on the DIS_TX bit in the TR_CONF2 register the internal local loop can be
transparent or non transparent to the S/T line.
– The external local loop (external Loop A) is activated in the same way as the internal
local loop described above. Additionally the EXLP bit in the TR_CONF0 register has
to be programmed and the loop has to be closed externally as described in Figure 28.
The S/T interface level detector is disabled.
This allows complete system diagnostics.
– In remote line loop (RLP) received data is looped back to the S/T interface. The Dchannel information received from the line card is transparently forwarded to the
output IOM-2 D-channel. The output B-channel information on IOM-2 is fixed to ‘FF’H
while this test loop is active. The remote loop is programmable in TR_CONF2.RLP.
Data Sheet
51
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
SX1
100 W
SX2
SCOUT-S(X)
SR1
100 W
SR2
Figure 28
External Loop at the S/T-Interface
– transmission of special test signals on the S/T interface according to the modified AMI
code are initiated via a C/I command written in CIX0 register (see Chapter 3.5.4)
Two kinds of test signals may be transmitted by the SBCX-X:
– The single pulses are of alternating polarity. One pulse is transmitted in each frame
resulting in a frequency of the fundamental mode of 2 kHz. The corresponding C/I
command is SSP (Send Single Pulses).
– The continuous pulses are of alternating polarity. 48 pulses are transmitted in each
frame resulting in a frequency of the fundamental mode of 96 kHz. The corresponding
C/I command is SCP (Send Continuous Pulses).
Data Sheet
52
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.4
Clock Generation
Figure 29 shows the clock system of the SBCX-X. The oscillator is used to generate a
7.68 MHz clock signal (fXTAL). In TE mode the DPLL generates the IOM-2 clocks FSC
(8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames.
In LT modes these pins are input and in LT-T mode an 1536 kHz clock synchronous to
S is output at SCLK which can be used for DCL input.
The FSC signal is used to generate the pulse lengths of the different reset sources C/I
Code, EAW pin and Watchdog (see Chapter 3.2.4).
FSC (TE mode)
XTAL
f XTAL
7.68 MHz
OSC
DCL (TE mode)
DPLL
BCL (TE mode)
SCLK (LT-T mode)
SW Reset
C/I
EAW
Watchdog
Pin RSTO
Reset
Generation
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
3081_06
Figure 29
Clock System of the SBCX-X
Data Sheet
53
2003-02-04
Data Sheet
54
o
general purpose
I/O pins
AUX0-2
o:768 kHz
(BCL)
BCL/SCLK
DD
o:1536 kHz
DCL
i
o:8 kHz
FSC
DU *4)
pin: MODE0=0
TE
Clock Modes
Selected via
Table 8
CH0-2:
strap pins for IOM
channel select *2)
o
i
o:1536 kHz
(SCLK) *3)
i:1536 kHz
(from SCLK)
or 4096 kHz
(from ext. PLL)
i:8 kHz
pin:MODE1=0
MODE0=1
LT-T
i
CH0-2:
strap pins for IOM
channel select *2)
CH0-2:
strap pins for IOM
channel select *2)
o
o:256 kHz or
768 kHz or
2048 kHz
(derived from
DCL/2)
i:512 kHz or
1536 kHz or
4096 kHz
i
o
o:256 kHz or
768 kHz or
2048 kHz
(derived from
DCL/2)
i:512 kHz or
1536 kHz or
4096 kHz
i:8 kHz
bit:MODE2=0
MODE1=1
MODE0=0
pin:MODE1=1
MODE0=1
i:8 kHz
NT
LT-S
general purpose
I/O pins
i
o
o:768 kHz
(derived from
DCL/2)
i:1536 kHz
i:8 kHz
bit:MODE2=1
MODE1=1
MODE0=1 or
MODE0=0 *1)
Int. NT
SBCX-X
PEB 3081
Description of Functional Blocks
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Note: The IOM-2 interface is adaptive. This means in LT-S/NT and LT-T mode other
frequencies for BCL and DCL are possible in the range of 512-4096 kHz
(DCL) and 256-2048 kHz (BCL). For details please refer to the application
note “Reconfigurable PBX”.
Note: i = input; o = output;
For all input clocks typical values are given although other clock frequencies may
be used, too.
1) The modes TE, LT-T and LT-S can directly be selected by strapping the pins
MODE1 and MODE0. The mode can be reprogrammed in TR_MODE.MODE2-0
where NT and intelligent NT can be selected additionally. In int. NT mode MODE0
selects between NT state machine (0) and LT-S state machine (1).
2) The number of IOM channels depends on the DCL clock, e.g. with
DCL=1536 kHz 3 IOM channels and with DCL=4096 kHz 8 channels are
available.
3) In LT-T mode the 1536 kHz output clock on SCLK is synchronous to the S
interface and can be used as input for the DCL clock.
4) The direction input/output refers to the direction of the B- and D-channel data
stream across the S-transceiver. Due to the capabilites of the IOM-2 handler the
direction of some other timeslots may be different if this is programmed by the host
(e.g. for data exchange between different devices connected to IOM-2).
Data Sheet
55
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.4.1
Description of the Receive PLL (DPLL)
The receive PLL performs phase tracking between the F/L transition of the receive signal
and the recovered clock. Phase adjustment is done by adding or subtracting 0.5 or 1
XTAL period to or from a 1.536-MHz clock cycle. The 1.536-MHz clock is than used to
generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to
have high or low times as short as 130 ns. After the S/T interface frame has achieved
the synchronized state (after three consecutive valid pairs of code violations) the FSC
output in TE mode is set to a specific phase relationship, thus causing once an irregular
FSC timing.
The phase relationships of the clocks are shown in Figure 30.
7.68 MHz
F-bit
1536 kHz *
* Synchronous to receive S/T. Duty Ratio 1:1 Normally
768 kHz
ITD09664
FSC
Figure 30
3.4.2
Phase Relationships of SBCX-X Clock Signals
Jitter
The timing extraction jitter of the SBCX-X conforms to ITU-T Recommendation I.430
(– 7% to + 7% of the S-interface bit period).
Data Sheet
56
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.4.3
Oscillator Clock Output C768
The SBCX-X derives its system clocks from an external clock connected to XTAL1 (while
XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and
XTAL2.
At pin C768 a buffered 7.68 MHz output clock is provided to drive further devices, which
is suitable in multiline applications for example (see Figure 31). This clock is not
synchronized to the S-interface.
In power down mode the C768 output is disabled (low signal).
7.68
MHz
XTAL1
XTAL2
C768
XTAL1
n.c.
n.c.
XTAL2
C768
XTAL1
n.c.
n.c.
XTAL2
C768
3086_12
Figure 31
Data Sheet
Buffered Oscillator Clock Output
57
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5
Control of Layer-1
The layer-1 activation / deactivation can be controlled by an internal state machine via
the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the
default state the internal layer-1 state machine of the SBCX-X is used.
By setting the L1SW bit in the TR_CONF0 register the internal state machine can be
disabled and the layer-1 commands, which are normally generated by the internal state
machine are written directly in the TR_CMD register or indications read from the
TR_STA register respectively.The SBCX-X layer-1 control flow is shown in Figure 32.
Figure 32
Layer-1 Control
In the following sections the layer-1 control by the SBCX-X state machine will be
described. For the description of the IOM-2 C/I0 channel see also Chapter 3.7.4.
The layer-1 functions are controlled by commands issued via the CIX0 register. These
commands, sent over the IOM-2 C/I channel 0 to layer-1, trigger certain procedures,
such as activation/deactivation, switching of test loops and transmission of special pulse
patterns. These procedures are governed by layer-1 state diagrams. Responses from
layer 1 are obtained by reading the CIR0 register after a CIC interrupt (ISTA).
The state diagrams of the SBCX-X are shown in Figure 34 and Figure 35. The
activation/deactivation implemented by the SBCX-X agrees with the requirements set
forth in ITU recommendations. State identifiers F1-F8 are in accordance with ITU I.430.
Data Sheet
58
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
State machines are the key to understanding the transceiver part of the SBCX-X. They
include all information relevant to the user and enable him to understand and predict the
behaviour of the SBCX-X. The state diagram notation is given in Figure 33. The
informations contained in the state diagrams are:
–
–
–
–
–
–
state name (based on ITU I.430)
S/T signal received (INFO)
S/T signal transmitted (INFO)
C/I code received
C/I code transmitted
transition criteria
The coding of the C/I commands and indications are described in detail in Chapter 3.5.4.
SBCX-X
IPAC
IPAC
OUT
IN
IOM-2 Interface
C /Ι
Ind.
Cmd.
Unconditional
Transition
State
S / T Interface
INFO
ix
ir
ITD09657
Figure 33
State Diagram Notation
The following example illustrates the use of a state diagram with an extract of the TE
state diagram. The state explained is “F3 deactivated”.
The state may be entered:
– from the unconditional states (ARL, RES, TM)
– from state “F3 pending deactivation”, “F3 power up”, “F4 pending activation” or “F5
unsynchronized” after the C/I command “DI” has been received.
The following informations are transmitted:
– INFO 0 (no signal) is sent on the S/T-interface.
– C/I message “DC” is issued on the IOM-2 interface.
Data Sheet
59
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
The state may be left by either of the following methods:
– Leave for the state “F3 power up” in case C/I = “TIM” code is received.
– Leave for state “F4 pending activation” in case C/I = AR8 or AR10 is received.
– Leave for the state “F6 synchronized” after INFO 2 has been recognized on the S/Tinterface.
– Leave for the state “F7 activated” after INFO 4 has been recognized on the S/Tinterface.
– Leave for any unconditional state if any unconditional C/I command is received.
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “*” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
The sections following the state diagram contain detailed information on all states and
signals used.
3.5.1
State Machine TE and LT-T Mode
3.5.1.1
State Transition Diagram (TE, LT-T)
Figure 34 shows the state transition diagram of the SBCX-X state machine. Figure 35
shows this for the unconditional transitions (Reset, Loop, Test Mode i).
Data Sheet
60
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
DC
i4
DI
F3
Deactivated
i0
TIM
i0
AR i2
DI
PU AR2)
AR
F4
Pending Act.
TIM
i0
i1
DI
RSY
i0
i2
i4
X
TIM
F5
Unsynchronized DI
i0
TIM
F3
Power Up
i0
i0
i4
PU
X
DI
Uncond. State
TIM
ix
i2
AR
X
X4)
F6
Synchronized
i0*TO1
i2
i3
ix
i4
RSY
i2
i4
X
F8
Lost Framing
i2
i0
i0
DI
TIM
i0*TO1
i2
DI*TO2
ix
AI3) AR2)
F7
Activated
i3
TO1:
TO2:
i4
i0*TO1
i4
DR1)
X
F3
Pending Deact.
i0
TIM*TO2
i0
16 ms
0.5 ms
1)
DR for transition from F7 or F8
DR6 for transition from F6
AR stands for AR8 or AR10
3)
AI stands for AI8 or AI10
4)
X stands for commands initiating unconditional
transitions (RES, ARL, SSP or SCP)
2)
Figure 34
Data Sheet
statem_te_s.vsd
State Transition Diagram (TE, LT-T)
61
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
SSP
SCP
ARL
TIM
SSP
TMA SCP
TIM
ARL ARL
DI
Test Mode i
DI
iti
RST
*
Loop A Closed
i3
TIM
DI
RES RES
Reset
i0
*
*
i3
i3
RES
TIM
DI
AIL ARL
RSY
Any
State
Loop A Activated
i3
*
statem_te_aloop_s.vsd
Figure 35
3.5.1.2
State Transition Diagram of Unconditional Transitions (TE, LT-T)
States (TE, LT-T)
F3 Pending Deactivation
State after deactivation from the S/T interface by INFO 0. Note that no activation from
the terminal side is possible starting from this state. A ’DI’ command has to be issued to
enter the state ’Deactivated State’.
F3 Deactivated State
The S/T interface is deactivated and the clocks are deactivated 500 µs after entering this
state and receiving INFO 0 if the CFS bit of the SBCX-X Configuration Register is set to
“0“. Activation is possible from the S/T interface and from the IOM-2 interface. The bit
TR_CMD.PD is set and the analog part is powered down.
F3 Power Up
The S/T interface is deactivated (INFO 0 on the line) and the clocks are running.
F4 Pending Activation
The SBCX-X transmits INFO 1 towards the network, waiting for INFO 2.
Data Sheet
62
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
F5 Unsynchronized
Any signal except INFO 2 or 4 detected on the S/T interface.
F6 Synchronized
The receiver has synchronized and detects INFO 2. INFO 3 is transmitted to
synchronize the NT.
F7 Activated
The receiver has synchronized and detects INFO 4. All user channels are now conveyed
transparently to the IOM-2 interface.
To transfer user channels transparently to the S/T interface either the command AR8 or
AR10 has to be issued and TR_STA.FSYN must be “1” (signal from remote side must
be synchronous).
F8 Lost Framing
The receiver has lost synchronization in the states F6 or F7 respectively.
Unconditional States
Loop A Closed (internal or external)
The SBCX-X loops back the transmitter to the receiver and activates by transmission of
INFO 3. The receiver has not yet synchronized.
For a non transparent internal loop the DIS_TX bit of register TR_CONF2 has to be set
to ’1’.
Loop A Activated (internal or external)
The receiver has synchronized to INFO 3. Data may be sent. The indication “AIL” is
output to indicate the activated state. If the loop is closed internally and the S/T line
awake detector detects any signal on the S/T interface, this is indicated by “RSY”.
Test Mode - SSP
Single alternating pulses are transmitted to the S/T-interface resulting in a frequency of
the fundamental mode of 2 kHz.
Test Mode - SCP
Continuous alternating pulses are transmitted to the S/T-interface resulting in a
frequency of the fundamental mode of 96 kHz.
Data Sheet
63
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5.1.3
C/I Codes (TE, LT-T)
Command
Abbr. Code Remark
Activation Request with
priority class 8
AR8
Activation Request with
priority class 10
AR10 1001 Activation requested by the SBCX-X,
D-channel priority set to 10 (see note)
Activation Request Loop
ARL
1010 Activation requested for the internal or
external Loop A (see note).
For a non transparent internal loop bit
DIS_TX of register TR_CONF2 has to be set
to ’1’ additionally.
Deactivation Indication
DI
1111 Deactivation Indication
Reset
RES
0001 Reset of the layer-1 statemachine
Timing
TIM
0000 Layer-2 device requires clocks to be
activated
Test mode SSP
SSP
0010 One AMI-coded pulse transmitted in each
frame, resulting in a frequency of the
fundamental mode of 2 kHz
Test mode SCP
SCP
0011 AMI-coded pulses transmitted continuously,
resulting in a frequency of the fundamental
mode of 96 kHz
1000 Activation requested by the SBCX-X,
D-channel priority set to 8 (see note)
Note: In the activated states (AI8, AI10 or AIL indication) the 2B+D channels are only
transferred transparently to the S/T interface if one of the three “Activation
Request” commands is permanently issued.
Data Sheet
64
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Indication
Abbr. Code Remark
Deactivation Request
DR
0000
Deactivation request via S/T-interface if left
from F7/F8
Reset
RES
0001
Reset acknowledge
Test Mode
Acknowledge
TMA
0010
Acknowledge for both SSP and SCP
Slip Detected
SLD
0011
Resynchronization
during level detect
RSY
0100
Signal received, receiver not synchronous
Deactivation Request
from F6
DR6
0101
Deactivation Request from state F6
Power up
PU
0111
IOM-2 interface clocking is provided
Activation request
AR
1000
INFO 2 received
Activation request loop
ARL
1010
Internal or external loop A closed
Illegal Code Violation
CVR
1011
Illegal code violation received. This function
has to be enabled by setting the EN_ICV bit of
register TR_CONF0.
Activation indication
loop
AIL
1110
Internal or external loop A activated
Activation indication
with priority class 8
AI8
1100
INFO 4 received,
D-channel priority is 8 or 9.
Activation indication
with priority class 10
AI10
1101
INFO 4 received,
D-channel priority is 10 or 11.
Deactivation
confirmation
DC
1111
Clocks are disabled if CFS bit of register
MODE1 is set to ’1’, quiescent state
Data Sheet
65
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5.1.4
Infos on S/T (TE, LT-T)
Receive Infos on S/T (Downstream)
Name
Abbr. Description
INFO 0
i0
No signal on S/T
INFO 2
i2
4 kHz frame
A=’0’
INFO 4
i4
4 kHz frame
A=’1’
INFO X
ix
Any signal except INFO 2 or INFO 4
Transmit Infos on S/T (Upstream)
Name
Abbr. Description
INFO 0
i0
No signal on S/T
INFO 1
i1
Continuous bit sequence of the form ’00111111’
INFO 3
i3
4 kHz frame
Test INFO 1
it1
SSP - Send Single Pulses
Test INFO 2
it2
SCP - Send Continuous Pulses
Data Sheet
66
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5.2
State Machine LT-S Mode
3.5.2.1
State Transition Diagram (LT-S)
RST
TIM RES
TIM
DR
Reset
i0
RES
DR
G4 Pend. Deact.
1)
ARD
*
DR
i0
DC
DI
ARD1)
Test Mode i
i0
it
(i0*16ms)+32ms
Any
State
SSP
TIM SCP
DC
*
SSP
SCP
Any
State
DR
G4 Wait for DR
i0
*
DC
DI DC
TIM 2)
DR
G1 Deactivated
i0
i0
(i0*8ms)+ARD1)
DC
AR ARD
G2 Pend. Act.
i2
DR
i3
i3
DC
RSY ARD
G2 Lost
Framing S/T
i2
i3
i3
AI
i3
DC
ARD
G3 Activated
i4
DR
i3
DR
1)
ARD = AR or ARL
2)
DI if i0
TIM if i0
s tatem_lts _s .v s d
Figure 36
State Transition Diagram (LT-S)
Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’
itself , i.e. C/I-code ’SSP/SCP’ must not be followed by C/I-code ’SCP/SSP’
directly.
Data Sheet
67
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5.2.2
States (LT-S)
G1 Deactivated
The transceiver is not transmitting. There is no signal detected on the S/T interface, and
no activation command is received in the C/I channel. The clocks are deactivated if
MODE1.CFS is set to 1. Activation is possible from the S/T interface and from the IOM2 interface.
G2 Pending Activation
As a result of an INFO 0 detected on the S/T line or an ARD command, the transceiver
begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise
reception of INFO 3 is to be implemented in software. In case of an ARL command, loop
2 is closed.
G3 Activated
Normal state where INFO 4 is transmitted to the S/T-interface. The transceiver remains
in this state as long as neither a deactivation nor a test mode is requested, nor the
receiver looses synchronism.
When receiver synchronism is lost, INFO 2 is sent automatically. After reception of
INFO 3, the transmitter keeps on sending INFO 4.
G2 Lost Framing
This state is reached when the transceiver has lost synchronism in the state G3
activated.
G4 Pending Deactivation
This state is triggered by a deactivation request DR. It is an unstable state: indication DI
(state “G4 Wait for DR.”) is issued by the transceiver when:
either INFO 0 is received for a duration of 16 ms,
or an internal timer of 32 ms expires.
G4 Wait for DR
Final state after a deactivation request. The transceiver remains in this state until DC is
issued.
Unconditional States
Test mode - SSP
Single alternating pulses are sent on the S/T-interface.
Data Sheet
68
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Test mode - SCP
Continuous alternating pulses are sent on the S/T-interface.
3.5.2.3
C/I Codes (LT-S)
Command
Abbr.
Code
Remark
Deactivation
Request
DR
0000
DR - Deactivation Request. Initiates a complete
deactivation from the exchange side by
transmitting INFO 0.
Reset
RES
0001
Reset of state machine. Transmission of
INFO 0. No reaction to incoming infos. RES is
an unconditional command.
Send Single Pulses
SSP
0010
Send Single Pulses.
Send Continuous
Pulses
SCP
0011
Send Continuous Pulses.
Activation Request
AR
1000
Activation Request. This command is used to
start an exchange initiated activation.
Activation Request
Loop
ARL
1010
Activation request loop. The transceiver is
requested to operate an analog loop-back close
to the S/T-interface.
Deactivation
Confirmation
DC
1111
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in which it
can be activated from a terminal (detection of
INFO 0 enabled).
Indication
Abbr.
Code
Remark
Timing
TIM
0000
Interim indication during activation procedure in
G1.
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous
Activation Request
AR
1000
INFO 0 received from terminal. Activation
proceeds.
Illegal Code
Violation
CVR
1011
Illegal code violation received. This function
has to be enabled in TR_CONF0.EN_ICV.
Data Sheet
69
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Indication
Code
Remark
Activation Indication AI
1100
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
1111
Timer (32 ms) expired or INFO 0 received for a
duration of 16 ms after deactivation request
3.5.2.4
Abbr.
DI
Infos on S/T (LT-S)
Receive Infos on S/T (Downstream)
I0
INFO 0 detected
I0
Level detected (signal different to I0)
I3
INFO 3 detected
I3
Any INFO other than INFO 3
Transmit Infos on S/T (Upstream)
I0
INFO 0
I2
INFO 2
I4
INFO 4
It
Send Single Pulses (SSP).
Send Continuous Pulses (SCP).
Data Sheet
70
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5.3
State Machine NT Mode
3.5.3.1
State Transition Diagram (NT)
RST
TIM RES
TIM
DR
Reset
i0
ARD
i0
DI
Any
State
ARD1)
SSP
TIM SCP
Test Mode i
i0
it
(i0*16ms)+32ms
DC
RES
DR
G4 Pend. Deact.
1)
*
DR
DC
DR
*
SSP
SCP
Any
State
G4 Wait for DR
i0
*
DC
DR
DI DC
TIM 3)
G1 Deactivated
ARD1)
i0
i0
(i0*8ms)
AR
DC
G1 i0 Detected
i0
DR
*
ARD1)
AR ARD
G2 Pend. Act
i2
DR
i3
i3
AID
RSY ARD
G2 Lost
Framing S/T
i2
i3
i3*ARD
AI
i3*ARD1)
i3*AID2)
ARD
G2 Wait for AID
RSY
i2
DR
i3
1)
AID2)
RSY
DR
RSY RSY
G3 Lost
Framing U
i2
*
ARD1)
AID2)
i3*AID2)
ARD1)
AI
AID
G3 Activated
RSY
ARD = AR or ARL
AID =AI or AIL
3)
DI if i0
TIM if i0
2)
i4
DR
i3
s tatem_n t_ s .v s d
Figure 37
Data Sheet
State Transition Diagram (NT)
71
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’
itself , i.e. C/I-code ’SSP/SCP’ must not be followed by C/I-code ’SCP/SSP’
directly.
3.5.3.2
States (NT)
G1 Deactivated
The transceiver is not transmitting. There is no signal detected on the S/T-interface, and
no activation command is received in the C/I channel. The clocks are deactivated if the
bit MODE1.CFS is set to 1. Activation is possible from the S/T interface and from the
IOM-2 interface.
G1 I0 Detected
An INFO 0 is detected on the S/T-interface, translated to an “Activation Request”
indication in the C/I channel. The transceiver is waiting for an AR command, which
normally indicates that the transmission line upstream (usually a two-wire U interface) is
synchronized.
G2 Pending Activation
As a result of the ARD command, an INFO 2 is sent on the S/T-interface. INFO 3 is not
yet received. In case of ARL command, loop 2 is closed.
G2 wait for AID
INFO 3 was received, INFO 2 continues to be transmitted while the transceiver waits for
a “switch-through” command AID from the device upstream.
G3 Activated
INFO 4 is sent on the S/T-interface as a result of the “switch through” command AID: the
B and D-channels are transparent. On the command AIL, loop 2 is closed.
G2 Lost Framing S/T
This state is reached when the transceiver has lost synchronism in the state G3
activated.
G3 Lost Framing U
On receiving an RSY command which usually indicates that synchronization has been
lost on the two-wire U interface, the transceiver transmits INFO 2.
Data Sheet
72
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
G4 Pending Deactivation
This state is triggered by a deactivation request DR, and is an unstable state. Indication
DI (state “G4 wait for DR”) is issued by the transceiver when:
either INFO 0 is received for a duration of 16 ms
or an internal timer of 32 ms expires.
G4 wait for DR
Final state after a deactivation request. The transceiver remains in this state until DC is
issued.
Unconditional States
Test Mode SSP
Send Single Pulses
Test Mode SCP
Send Continuous Pulses
3.5.3.3
C/I Codes (NT)
Command
Abbr.
Code
Remark
Deactivation
Request
DR
0000
DR - Deactivation Request. Initiates a complete
deactivation from the exchange side by
transmitting INFO 0. Unconditional command.
Reset
RES
0001
Reset of state machine. Transmission of
INFO 0. No reaction to incoming infos. RES is
an unconditional command.
Send Single Pulses
SSP
0010
Send Single Pulses.
Send Continuous
Pulses
SCP
0011
Send Continuous Pulses.
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous
Activation Request
AR
1000
Activation Request. This command is used to
start an exchange initiated activation.
Activation Request
Loop
ARL
1010
Activation request loop. The transceiver is
requested to operate an analog loop-back close
to the S/T-interface.
Data Sheet
73
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Command
Code
Remark
Activation Indication AI
1100
Synchronous receiver, i.e. activation
completed.
Activation Indication AIL
Loop
1110
Activation Indication Loop
Deactivation
Confirmation
DC
1111
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in which it
can be activated from a terminal (detection of
INFO 0 enabled).
Indication
Abbr.
Code
Remark
Timing
TIM
0000
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous
Activation Request
AR
1000
INFO 0 received from terminal. Activation
proceeds.
Illegal Code
Violation
CVR
1011
Illegal code violation received. This function
has to be enabled in TR_CONF0.EN_ICV.
Activation Indication AI
1100
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
1111
Timer (32 ms) expired or INFO 0 received for a
duration of 16 ms after deactivation request
Data Sheet
Abbr.
DI
Interim indication during deactivation procedure
74
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5.4
Command / Indicate Channel Codes (C/I0) - Overview
The table below presents all defined C/I0 codes. A command needs to be applied
continuously until the desired action has been initiated. Indications are strictly state
orientated. Refer to the state diagrams in the previous sections for commands and
indications applicable in various states.
Code
TE/LT-T
LT-S
NT
Cmd
Ind
Cmd
Ind
Cmd
Ind
0
0
0
0
TIM
DR
DR
TIM
DR
TIM
0
0
0
1
RES
RES
RES
–
RES
–
0
0
1
0
SSP
TMA
SSP
–
SSP
–
0
0
1
1
SCP
SLD
SCP
–
SCP
–
0
1
0
0
–
RSY
–
RSY
RSY
RSY
0
1
0
1
–
DR6
–
–
–
–
0
1
1
0
–
–
–
–
–
–
0
1
1
1
–
PU
–
–
–
–
1
0
0
0
AR8
AR
AR
AR
AR
AR
1
0
0
1
AR10
–
–
–
–
–
1
0
1
0
ARL
ARL
ARL
–
ARL
–
1
0
1
1
–
CVR
–
CVR
–
CVR
1
1
0
0
–
AI8
–
AI
AI
AI
1
1
0
1
–
AI10
–
–
–
–
1
1
1
0
–
AIL
–
–
AIL
–
1
1
1
1
DI
DC
DC
DI
DC
DI
Data Sheet
75
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.6
Control Procedures
3.6.1
Example of Activation/Deactivation
An example of an activation/deactivation of the S/T interface initiated by the terminal with
the time relationships mentioned in the previous chapters is shown in Figure 38.
NT/Linecard
TE
INFO 0
INFO 1
RSY
max. 6 ms
AR
INFO 2
INFO 3
AR
0.5 ms
INFO 4
AI
DR
16 ms
INFO 0
INFO 0
A_DEACT.DRW
Figure 38
Data Sheet
Example of Activation/Deactivation Initiated by the Terminal
76
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.6.2
Activation initiated by the Terminal
INFO 1 has to be transmitted as long as INFO 0 is received.
INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is
received.
After reception of INFO 2 or INFO 4 transmission of INFO 3 has to be started.
Data can be transmitted if INFO 4 has been received.
µC Interface
TE
S/T Interface
NT
INFO 0
TDDIS='1', XINF='010'
INFO 1
INFO 2
RINF='01'
XINF='000'
T1TE
INFO 0
RINF='10'
INFO 3
XINF='011'
INFO 4
RINF='11'
T2TE
TDDIS='0'
INFO 0
RINF='00'
TDDIS='1', XINF='000'
T3TE
INFO 0
INFO 0
T1TE: 2 to 6 frames (0.5 ms to 1.5 ms)
T2TE:
2 frames (0.5 ms)
4 frames (1 ms)
T3TE:
act_deac_te-ext_s.vsd
Figure 39
Example of Activation/Deactivation initiated by the Terminal (TE).
Activation/Deactivation completely under Software Control
Note: RINF and XINF are Receive- and Transmit-INFOs of the registers TR_STA
TR_CMD.
Data Sheet
77
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.6.3
Activation initiated by the Network Termination NT
INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received.
After reception of INFO 2 or INFO 4 transmission of INFO 3 has to be started.
Data can be transmitted if INFO 4 has been received.
µC Interface
TE
S/T Interface
NT
INFO 0
RINF='01'
INFO 2
T1TE
RINF='10'
TDDIS='1', XINF='011'
INFO 3
INFO 4
RINF='11'
T2TE
TDDIS='0'
INFO 0
RINF='00'
T3TE
TDDIS='1', XINF='000'
INFO 0
INFO 0
T1TE: 2 to 6 S/T frames (0.5 ms to 1.5 ms)
2 S/T frames (0.5 ms)
T2TE:
4 S/T frames (1 ms)
T3TE:
act_deac_lt_ext_s.vsd
Figure 40
Example of Activation/Deactivation initiated by the Network
Termination (NT).
Activation/Deactivation completely under Software Control
Note: RINF and XINF are Receive- and Transmit-INFOs of the registers TR_STA
TR_CMD.
Data Sheet
78
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.7
IOM-2 Interface
The SBCX-X supports the IOM-2 interface in linecard mode and in terminal mode with
single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD
and DU. The rising edge of FSC indicates the start of an IOM-2 frame. The DCL and the
BCL clock signals synchronize the data transfer on both data lines DU and DD. The DCL
is twice the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the
rising edge of the first DCL clock cycle and sampled at the falling edge of the second
clock cycle.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register.
TE Mode
A DCL signal and BCL signal (pin BCL/SCLK) output is provided and the FSC signal is
generated by the receive DPLL which synchronizes it to the received S/T frame.
The BCL clock together with the two serial data strobe signals (SDS1, SDS2) can be
used to connect time slot oriented standard devices to the IOM-2 interface. If the
transceiver is disabled (TR_CON.DIS_TR) the DCL and FSC pins become input. In this
case the clock mode bit (IOM_CR.CLKM) selects between a double clock and a single
clock input for DCL.
The clock rate/frequency of the IOM-2 signals in TE mode are:
DD, DU:
768 kbit/s
FSC (o):
8 kHz
DCL (o):
1536 kHz (double clock rate)
BCL (o):
768 kHz (single clock rate)
Option - Transceiver disabled (DIS_TR = ’1’):
FSC (i):
8 kHz
DCL (i):
1536 ... 4096 kHz, in steps of 512 kHz (double clock rate)
LT-S, LT-T, NT, iNT Mode
The IOM-2 clock signals FSC and BCL are input.
In LT-T mode a 1536 kHz output clock synchronous to S is provided at pin SCLK which
can directly be connected to the DCL input.
DD, DU:
FSC (i):
DCL (i):
SCLK (o):
data rate = DCL/2 kbit/s (LT-T mode)
8 kHz
512 ... 4096 kHz, in steps of 512 kHz (double clock rate)
1536 kHz (LT-T mode), BCL derived via DCL/2 (LT-S/NT mode)
Note: In all modes the direction of the data lines DU and DD is not fix but depending on
the timeslot which can be seen in the figures below.
Data Sheet
79
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
IOM-2 Frame Structure (TE Mode)
The frame structure on the IOM-2 data ports (DU, DD) of a master device in IOM-2
terminal mode is shown in Figure 41.
Figure 41
IOMÒ-2 Frame Structure in Terminal Mode
The frame is composed of three channels
• Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR
programming channel (MON0) and a command/indication channel (CI0) for control
and programming of the layer-1 transceiver.
• Channel 1 contains two 64-kbit/s intercommunication channels (IC) plus a MONITOR
and command/indicate channel (MON1, CI1) to program or transfer data to other
IOM-2 devices.
• Channel 2 is used for the TlC-bus access. Only the command/indicate bits are
specified in this channel.
Data Sheet
80
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
IOM-2 Frame Structure (LT-S, LT-T Modes)
This mode is used in LT-S and LT-T applications. The frame is a multiplex of up to eight
IOM-2 channels (DCL = 4096 kHz, see Figure 42), each of which has the structure
described above.
The reset value for assignment to one of the eight channels (0 to 7) is done via pin
strapping (CH0-2), however the host can reprogram the selected timeslot in
DCH_TSDP.TSS.
125 µ s
FSC
DCL
DD
IOM R CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0
DU
IOM CH0
R
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0
B1
Figure 42
B2
MONITOR
D
C/I
MM
RX
ITD09635
Multiplexed Frame Structure of the IOM-2 Interface
in Non-TE Timing Mode
IOM-2 Frame Structure (NT Mode)
In NT mode one IOM-2 channel is used (DCL=512 kHz). The channel structure is the
same as described above.
Data Sheet
81
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.7.1
IOM-2 Handler
The IOM-2 handler offers a great flexibility for handling the data transfer between the
different functional units of the SBCX-X and voice/data devices connected to the IOM-2
interface. Additionally it provides a microcontroller access to all timeslots of the IOM-2
interface via the four controller data access registers (CDA). Figure 43 shows the
architecture of the IOM-2 handler. For illustrating the functional description it contains all
configuration and control registers of the IOM-2 handler. A detailed register description
can be found in Chapter 4.3.
The PCM data of the functional units
• Transceiver (TR) and the
• Controller data access (CDA)
can be configured by programming the time slot and data port selection registers
(TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can
be assigned to each of the 32 PCM time slots of the IOM-2 frame. With the DPS bit (Data
Port Selection) the output of each functional unit is assigned to DU or DD respectively.
The input is assigned vice versa. With the data control registers (xxx_CR) the access to
the data of the functional units can be controlled by setting the corresponding control bits
(EN, SWAP).
The IOM-2 handler also provides access to the
• MONITOR channel (MON)
• C/I channels (C/I0, C/I1) and
• TIC bus (TIC)
The access to these channels is controlled by the register MON_CR and DCI_CR.
The IOM-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the
control registers IOM_CR, SDS1_CR and SDS2_CR.
The reset configuration of the SBCX-X IOM-2 handler corresponds to the defined frame
structure and data ports of a master device in IOM-2 terminal mode (see Figure 41).
Data Sheet
82
2003-02-04
83
CDA_TSDPxy
CDAx_CRx
MCDA
STI
MSTI
ASTI
( DPS, TSS,
EN_TBM, SWAP,
EN_I1/0, EN_O1/0,
MCDAxy, STIxy,
STOVxy, ACKxy )
CDA Control
CDA Data
BCL / SCLK
FSC
DD
DU
MON Handler
IOM-2 Interface
Microcontroller Interface
C/I0
Data
TIC
C/I1
DCI_CR
(DPS_CI1,
EN_CI1)
(CS2-0)
DCIC_CR
C/I1
C/I Data Control
C/I0
IOM_CR
(TIC_DIS)
(DPS, CS2-0,
EN_MON)
MON_CR
TIC Bus
Disable
Monitor Data
EN_BCL, CLKM, DIS_OD, DIS_IOM,
DIOM_INV, DIOM_SDS
DCL
TIC Bus Data
Control
Monitor Data
Note: The registers shown above are used to control
the corresponding functional block (e.g. programming
of timeslot, data port, enabling/disabling, etc.)
CDA10
CDA11
CDA20
CDA21
CDA Registers
Controller Data Access (CDA)
IOM_CR
SDS1_CR
SDS2_CR
C/I0 Data
Data Sheet
C/I1 Data
Figure 43
SDS2
SDS1
( ENS_TSS, ENS_TSS+1,
ENS_TSS+3, TSS, SDS_BCL
TR_TSDP_BC1
TR_TSDP_BC2
TRC_CR
(DPS, TSS,
CS2-0, EN_D,
EN_B1R,
EN_B1X,
EN_B2R,
EN_B2X )
Control
Transceiver
Data Access
D, B1, B2, C/I0 Data
IOM-2 Handler
3186_07
D-channel RX/TX
B1-channel RX
B1-channel TX
B2-channel RX
B2-channel TX
Transceiver
Data TR
SBCX-X
PEB 3081
Description of Functional Blocks
.
Architecture of the IOM Handler (Example Configuration)
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.7.1.1
Controller Data Access (CDA)
With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the
SBCX-X IOM-2 handler provides a very flexible solution for the host access to up to 32
IOM-2 time slots.
The functional unit CDA (controller data access) allows with its control and configuration
registers
• looping of up to four independent PCM channels from DU to DD or vice versa over the
four CDA registers
• shifting of two independent PCM channels to another two independent PCM channels
on both data ports (DU, DD). Between reading and writing the data can be
manipulated (processed with an algorithm) by the microcontroller. If this is not the
case a switching function is performed
• monitoring of up to four time slots on the IOM-2 interface simultaneously
• microcontroller read and write access to each PCM timeslot
The access principle which is identical for the two channel register pairs CDA10/11 and
CDA20/21 is illustrated in Figure 44. Each of the index variables x,y used in the following
description can be 1 or 2 for x and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a TSDPxy register is assigned by which the
time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a
time slot from 0...31 can be selected. With the DPS (Data Port Selection) bit the output
of the CDAxy register can be assigned to DU or DD respectively. The time slot and data
port for the output of CDAxy is always defined by its own TSDPxy register. The input of
CDAxy depends on the SWAP bit in the control registers CRx.
• If the SWAP bit = ’0’ (swap is disabled) the time slot and data port for the input and
output of the CDAxy register is defined by its own TSDPxy register.
• If the SWAP bit = ’1’ (swap is enabled) the input port and timeslot of the CDAx0 is
defined by the TSDP register of CDAx1 and the input port and timeslot of CDAx1 is
defined by the TSDP register of CDAx0. The input definition for timeslot and data port
CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output
timeslots are not affected by SWAP.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
Usually one input and one output of a functional unit (transceiver, HDLC controller, CDA
register) is programmed to a timeslot on IOM-2 (e.g. for B-channel transmission in
upstream direction the HDLC controller writes data onto IOM and the transceiver reads
data from IOM). For monitoring data in such cases a CDA register is programmed as
described below under “Monitoring Data”. Besides that none of the IOM timeslots must
be assigned more than one input and output of any functional unit.
Data Sheet
84
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
.
TSa
TSb
DU
Control
Register
1
CDAx0
0
1
1
1
1
1
CDAx1
1
1
0
CDA_TSDPx1
Enable
input *
output
(EN_I1)
(EN_O1)
Input
Swap
(SWAP)
input *
(EN_I0)
1
Time Slot
Selection (TSS)
0
Data Port
Selection (DPS)
Time Slot
Selection (TSS)
CDA_CRx
0
Enable
output
(EN_O0)
Data Port
Selection (DPS)
CDA_TSDPx0
1
DD
TSa
TSb
IOM_HAND.FM4
x = 1 or 2; a,b = 0...31
*) In the normal mode (SWAP=0) the input of CDAx0 and CDAx1 is enabled via EN_I0 and
EN_I1, respectively. If SWAP=1 EN_I0 controls the input of CDAx1 and EN_I1 controls the
input of CDAx0. The output control (EN_O0 and EN_O1) is not affected by SWAP.
Figure 44
Data Access via CDAx1 and CDAx2 Register Pairs
Looping and Shifting Data
Figure 45 gives examples for typical configurations with the above explained control and
configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers
TSDPxy or CDAx_CR:
a) looping IOM-2 time slot data from DU to DD or vice versa (SWAP = 0)
b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP
= 1)
c) switching data from TSa to TSb and looping from DU to DD or TSc to TSd and looping
from DD to DU respectively
TSa is programmed in TSDP10, TSb in TSDP11, TSc in TSDP20 and TSd in TSDP21.
It should also be noted that the input control of CDA registers is swapped if SWAP=1
while the output control is not affected (e.g. for CDA11 in example a: EN_I1=1 and
EN_O1=1, whereas for CDA11 in example b: EN_I0=1 and EN_O1=1).
Data Sheet
85
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
a) Looping Data
TSa
TSb
TSc
TSd
CDA10
CDA11
CDA20
CDA21
TSc
’1’
TSd
’1’
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’0’
.SWAP
’0’
’0’
b) Shifting Data
TSa
TSb
TSc
TSd
CDA10
CDA11
CDA20
CDA21
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’1’
.SWAP
’1’
c) Switching Data
TSa
TSb
CDA10
CDA11
TSc
’0’
TSd
’1’
’1’
TSc
TSd
CDA20
CDA21
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’0’
.SWAP
’1’
Figure 45
TSc
’1’
TSd
’1’
’1’
Examples for Data Access via CDAxy Registers
a) Looping Data
b) Shifting (Switching) Data
c) Switching and Looping Data
Data Sheet
86
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Figure 46 shows the timing of looping TSa from DU to DD (a = 0...31) via CDAxy
register. TSa is read in the CDAxy register from DU and is written one frame later on DD.
.
a = 0...31
FSC
DU
TSa
TSa
µC *)
DD
TSa
STOV
ACK
WR
RD
STI
CDAxy
TSa
*) if access by the µC is required
Figure 46
Data Access when Looping TSa from DU to DD
Figure 47 shows the timing of shifting data from TSa to TSb on DU (DD). In Figure 47a)
shifting is done in one frame because TSa and TSb didn’t succeed direct one another (a,
b = 0...29 and b ³ a+2. In Figure 47b) shifting is done from one frame to the following
frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller
than a (b < a).
At looping and shifting the data can be accessed by the controller between the
synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and
STOV are explained in the section ’Synchronous Transfer’. If there is no controller
intervention the looping and shifting is done autonomous.
Data Sheet
87
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
a) Shifting TSa ® TSb within one frame
(a,b: 0...31 and b ³ a+2)
FSC
DU
(DD)
TSa
TSa
TSb
µC *)
STI
STOV
ACK
WR
RD
STI
CDAxy
b) Shifting TSa ® TSb in the next frame
(a,b: 0...31 and (b = a+1 or b
工商网监
湘ICP备2023018690号
